The present invention relates to a clock synchronizing circuit and, more particularly, to a clock synchronizing circuit for use with a demodulator in a digital carrier wave transmission system.
In a demodulator applicable to a digital carrier wave transmission system, a clock signal must be provided in order that a demodulated analog signal may be sampled at optimum points and thereby converted to a digital signal, i.e., a regenerated digital signal. A prior art clock synchronizing circuit which is adapted for recovery of the clock signal comprises a clock separating means or clock component producing means including a tank circuit, a limiter, a phase comparator, and a voltage controlled oscillator (VCO). The clock separating means separates or produces a clock component from a digital modulated wave (e.g. PSK wave or QAM wave) or a demodulated analog signal. The limiter is adapted to limit the amplitude variation of the separated clock component. The phase comparator compares an output of the limiter and an output of the VCO in terms of phase, producing an error voltage which is proportional to the phase difference. Controlled by the error voltage, the VCO varies its oscillation frequency until the error voltage becomes minimum, that is, until a clock signal recovered by the VCO is brought into synchronism with the separated clock component. The recovered clock signal which is synchronized, as stated, is used to sample the previously mentioned demodulated signal.
The prior art clock synchronizing circuit requires the limiter thereof to be furnished with, among other things, a small amount of AM/PM conversion. It is difficult to realize a limiter with a small amount of AM/PM conversion, at the present stage of the art. Although such a limiter may be implemented with a high-speed IC gate, it is expensive and needs precise and difficult to make adjustments.